After a short description of the ISTI's HPCLab and a highlight on the research
activities conducted, we present a fast sorting algorithm implementing an
efficient bitonic sorting network on graphics processors.  Sorting is a
fundamental and universal problem in computer science. Even if sort has been
extensively addressed by many research works, it still remains an interesting
challenge to make it faster by exploiting novel technologies. In this light, the
presentation shows how to use graphics processors as coprocessors to speed up
sorting while allowing CPU to perform other tasks. Our new algorithm exploits a
memory-efficient data access pattern maintaining the minimum number of accesses
to the memory out of the chip. We introduce an efficient instruction dispatch
mechanism to improve the overall sorting performance.